This invention relates generally to differential amplifier circuits and more particularly to comparators which include such differential amplifier circuits.
As is known in the art, many comparator circuits include a differential amplifier circuit as an input stage thereof. In order to provide a relatively wide bandwidth amplifier circuit using standard integrated circuit processing techniques, such differential amplifier circuit usually includes a pair of n-p-n transistors arranged with their base electrodes adapted for coupling to an input signal and with their emitter electrodes connected to a common current source. In order to provide a relatively high gain to the input signal, it is frequently desired to provide a multi-stage comparator. When n-p-n transistors are used in such multi-stage comparator circuit, however, the DC level of the input signal is shifted towards the positive collector voltage supply, typically referred to as +V.sub.cc. Consequently, such multi-stage comparator circuit typically includes a level shifter following the amplifier stage to shift the DC level of the amplified signal negatively. Typically, the level shifter circuit includes Zener diodes. One technique used to reduce the effect of poor processing caused matching of the Zener diode is to provide buried Zener diodes after the first gain stage as described in an article entitled "A Fast, Latching Comparator for 12 Bit A/D Applications", by G. Erdi, IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 6, December 1980. The use of buried Zener diodes, however, requires a deviation from standard integrated circuit processing techniques.